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16-mbit (1m x 16) static ram CY62167DV30 mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05328 rev. *g revised july 27, 2006 features ? tsop i configurable as 1m x 16 or as 2m x 8 sram ? very high speed: 45 ns ? wide voltage range: 2.2v ? 3.6v ? ultra-low active power ? typical active current: 2 ma @ f = 1 mhz ? typical active current: 18.5 ma @ f = f max (45 ns speed) ? ultra-low standby power ? easy memory expansion with ce 1 , ce 2 and oe features ? automatic power-down when deselected ? cmos for optimum speed/power ? available in pb-free and non pb-free 48-ball vfbga and 48-pin tsop i package functional description [1] the CY62167DV30 is a high-performance cmos static ram organized as 1m words by 16 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-dow n feature that significantly reduces power consumption by 99% when addresses are not toggling. the device can also be put into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce 1 low, ce 2 high and we low). writing to the device is accomplished by taking chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). reading from the device is accomplished by taking chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. note: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram 1m 16 / 2m x 8 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 power-down circuit bhe ble ce 2 ce 1 ce 2 ce 1 a 19 byte
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 2 of 12 product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1mhz f = f max min. typ. [2] max. typ. [2] max. typ. [2] max. typ. [2] max. CY62167DV30ll 2.2 3.0 3.6 45 2 4 18.5 37 2.5 22 55 15 30 70 12 25 pin configuration [3, 4, 5] we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 dnu 3 2 6 5 4 1 d e b a c f g h a 16 dnu vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we ce2 dnu bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss i/o15/a20 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe vss ce1 a0 48-pin tsop i (forward) (1m x 16/ 2m x 8) top view n otes: 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. 3. nc pins are not connected on the die. 4. dnu pins have to be left floating. 5. ball h6 for the fbga package can be used to upgrade to a 32m density. 6. the byte pin in the 48-tsop i package has to be tied to v cc to use the device as a 1m x 16 sram. the 48-tsopi package can also be used as a 2m x 8 sram by tying the byte signal to v ss . in the 2m x 8 configuration, pin 45 is a20, while bhe , ble and i/o8 to i/o14 pins are not used (dnu). [6] 48-ball vfbga top view
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 3 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .. .............. .............. ....?65c to +150c ambient temperature with power applied .............................................?55c to +125c supply voltage to ground potential ...... ?0.2v to v cc + 0.3v dc voltage applied to outputs in high-z state [7, 8] ................................ ?0.2v to v cc + 0.3v dc input voltage [7, 8] ............................. ?0.2v to v cc + 0.3v output current into outputs (low) .............................20 ma static discharge voltage ........... .............. ................. > 2001v (per mil-std-883, method 3015) latch-up current .....................................................> 200 ma operating range device range ambient temperature v cc [9] CY62167DV30ll industrial ?40c to +85c 2.20v to 3.60v electrical characteristics over the operating range parameter description test conditions CY62167DV30-45 CY62167DV30-55 CY62167DV30-70 unit min. typ. [2] max. min. typ. [2] max. min. typ. [2] max. v oh output high voltage i oh = ?0.1 ma v cc = 2.20v 2.0 2.0 2.0 v i oh = ?1.0 ma v cc = 2.70v 2.4 2.4 2.4 v ol output low voltage i ol = 0.1 ma v cc = 2.20v 0.4 0.4 0.4 v i ol = 2.1ma v cc = 2.70v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc +0.3v 1.8 v cc +0.3v 1.8 v cc +0.3v v v cc = 2.7v to 3.6v 2.2 2.2 2.2 v il input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 ?0.3 0.6 ?0.3 0.6 v v cc = 2.7v to 3.6v 0.8 0.8 0.8 i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = v cc(max) i out = 0 ma cmos levels f = f max = 1/t rc 18.5 37 15 30 12 25 ma f = 1 mhz 2 4 2 4 2 4 i sb1 automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v, v in < 0.2v, f = f max (address and data only), f = 0 (oe , we , bhe, ble ), v cc = 3.60v 2.5 22 2.5 22 2.5 22 a i sb2 automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v 2.5 22 2.5 22 2.5 22 a notes: 7. v il(min.) = ?2.0v for pulse durations less than 20 ns. 8. v ih(max) = v cc + 0.75v for pulse durations less than 20 ns. 9. full device ac operation requires linear v cc ramp from 0 to v cc(min.) and v cc must be stable at v cc(min) for 500 s.
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 4 of 12 notes: 10. tested initially and after any design or proc ess changes that may affect these parameters. 11. this applies for all packages. 12. test condition for the 45 ns part is with a load capacitance of 30 pf. 13. full device operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) > 100 s. capacitance [10, 11] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 8pf c out output capacitance 10 pf thermal resistance [10] parameter description test co nditions vfbga tsop i unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, 2-layer printed circuit board 55 60 c/w jc thermal resistance (junction to case) 16 4.3 c/w ac test loads and waveforms [12] v cc v cc output r2 50 pf [12] including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: the venin equivalent all input pulses r th r1 parameters 2.5v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min. typ. [2] max. unit v dr v cc for data retention 1.5 v i ccdr data retention current v cc = 1.5v ce 1 > v cc ? 0.2v, ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v 10 a t cdr [10] chip deselect to data retention time 0 ns t r [13] operation recovery time t rc ns
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 5 of 12 data retention waveform [14] switching characteristics over the operating range [15] parameter description 45 ns [12] 55 ns 70 ns unit min. max. min. max. min. max. read cycle t rc read cycle time 45 55 70 ns t aa address to data valid 45 55 70 ns t oha data hold from address change 10 10 10 ns t ace ce 1 low and ce 2 high to data valid 45 55 70 ns t doe oe low to data valid 25 25 35 ns t lzoe oe low to low z [16] 555 ns t hzoe oe high to high z [16, 17] 15 20 25 ns t lzce ce 1 low and ce 2 high to low z [16] 10 10 10 ns t hzce ce 1 high and ce 2 low to high z [16, 17] 20 20 25 ns t pu ce 1 low and ce 2 high to power-up 0 0 0 ns t pd ce 1 high and ce 2 low to power-down 45 55 70 ns t dbe ble/bhe low to data valid 45 55 70 ns t lzbe ble /bhe low to low z [16] 10 10 10 ns t hzbe ble /b he high to high z [16, 17] 15 20 25 ns write cycle [18] t wc write cycle time 45 55 70 ns t sce ce 1 low and ce 2 high to write end 40 40 60 ns t aw address set-up to write end 40 40 60 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 35 40 45 ns t bw ble /bhe low to write end 40 40 60 ns t sd data set-up to write end 25 25 30 ns t hd data hold from write end 0 0 0 ns t hzwe we low to high-z [16, 17] 15 20 25 ns t lzwe we high to low-z [16] 10 10 10 ns notes: 14. bhe .ble is the and of both bhe and ble . chip can be deselected by either disabling t he chip enable signals or by disabling both bhe and ble . 15. test conditions for all parameters other than tri-state parame ters assume signal transition time of 1 ns/v, timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 16. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 17. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 18. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be refer enced to the edge of the signal that terminates the write. v cc , min. v cc , min. t cdr v dr > 1.5 v data retention mode t r ce 1 or v cc bhe , ble or ce 2
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 6 of 12 switching waveforms read cycle 1 (address transition controlled) [19, 20] read cycle 2 (oe controlled) [20, 21] notes: 19. the device is contin uously selected. oe , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . 20. we is high for read cycle. 21. address valid prior to or coincident with ce 1 , bhe , ble transition low and ce 2 transition high. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe high i cc i sb impedanc e oe ce 1 address v cc supply current bhe /ble data out ce 2
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 7 of 12 write cycle 1 (we controlled) [18, 22, 23, 24] notes: 22. data i/o is high-impedance if oe = v ih . 23. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high-impedance state. 24. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw see note 23 address we data i/o oe bhe /ble ce 1 ce 2
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 8 of 12 write cycle 2 (ce 1 or ce 2 controlled) [18, 22, 23, 24] write cycle 3 (we controlled, oe low) [23, 24] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data see note 23 t bw t sa ce 1 address we data i/o oe bhe /ble ce 2 valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw see note 23 ce 1 address ce 2 we data i/o bhe /ble
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 9 of 12 write cycle 4 (bhe /ble controlled, oe low) [23, 24] truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power h x x x x x high z deselect/power-down standby (i sb ) x l x x x x high z deselect/power-down standby (i sb ) x x x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l high z (i/o 8 ?i/o 15 ); data out (i/o 0 ?i/o 7 ) read active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) read active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) lhlxhlhigh z (i/o 8 ?i/o 15 ); data in (i/o 0 ?i/o 7 ) write active (i cc ) l h l x l h data in (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) write active (i cc ) l h h h l h high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) switching waveforms (continued) t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe see note 23 data i/o address ce 1 we bhe /ble ce 2
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 10 of 12 ordering information speed (ns) ordering code package diagram package type operating range 45 CY62167DV30ll-45zxi 51-85183 48-pin tsop i (12 x 18.4 x 1 mm) (pb-free) industrial 55 CY62167DV30ll-55bvi 51-85178 48-ball fine pitch bga (8 x 9.5 x 1 mm) CY62167DV30ll-55bvxi 48-ball fine pitch bga (8 x 9.5 x 1 mm) (pb-free) CY62167DV30ll-55zi 51-85183 48-pin tsop i (12 x 18.4 x 1 mm) CY62167DV30ll-55zxi 48-pin tsop i (12 x 18.4 x 1 mm) (pb-free) 70 CY62167DV30ll-70bvi 51-85178 48-ball fine pitch bga (8 x 9.5 x 1 mm) please contact your local cypress sales re presentative for availability of these parts package diagrams a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25mcab ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 8.000.10 9.500.10 a 9.500.10 8.000.10 b 1.875 2.625 0.26 max. 48-ball vfbga (8 x 9.5 x 1 mm) (51-85178) 51-85178-**
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 11 of 12 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark and more battery life is a trademark of cypress semiconductor corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagrams (continued) 1 n 0.020[0.50] 0.007[0.17] 0.037[0.95] 0.002[0.05] 0-5 max. 0.028[0.70] 0.010[0.25] 0.004[0.10] 0.011[0.27] 0.041[1.05] 0.047[1.20] 0.472[12.00] 0.724 [18.40] 0.787[20.00] 0.006[0.15] typ. 0.020[0.50] 0.008[0.21] gauge plane seating plane 0.004[0.10] dimensions in inches[mm] min. max. jedec # mo-142 48-pin tsop i (12 x 18.4 x 1mm) (51-85183) 51-85183-*a
CY62167DV30 mobl ? document #: 38-05328 rev. *g page 12 of 12 document history page document title: CY62167DV30 mobl ? , 16-mbit (1m x 16) static ram document number: 38-05328 rev. ecn no. issue date orig. of change description of change ** 118408 09/30/02 gug new data sheet *a 123692 02/11/03 dpm changed advanced to preliminary added package diagram *b 126555 04/25/03 dpm minor change: chang ed sunset owner from dpm to hrt *c 127841 09/10/03 xrj added 48 tsop i package *d 205701 aju changed byte pin usage description for 48 tsopi package *e 238050 see ecn kkv/aju replaced 48 -ball vfbga package diagram; modified package name in ordering information table from bv48a to bv48b *f 304054 see ecn pci added 45-ns speed bin in ac, dc and ordering information tables added footnote #12 on page #4 added pb-free packages on page # 10 *g 492895 see ecn vkn modified datasheet to explain x8 configurability removed l power bin from the product offering updated ordering information table

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